Host device with path selection modification responsive to mismatch in initiator-target negotiated rates

ABSTRACT

An apparatus comprises at least one processing device that includes a processor coupled to a memory. The processing device is configured to control delivery of input-output (IO) operations from a host device to at least one storage system over selected ones of a plurality of paths through a network, wherein the paths are associated with respective initiator-target pairs, the initiators being implemented on the host device and the targets being implemented on the storage system. The processing device is further configured to identify one or more of the plurality of paths that each exhibits at least a threshold amount of mismatch between a negotiated rate of its initiator and a negotiated rate of its target, and to modify path selection in the host device to at least temporarily avoid selecting the one or more identified paths. The processing device illustratively comprises at least a portion of the host device.

FIELD

The field relates generally to information processing systems, and more particularly to storage in information processing systems.

BACKGROUND

Storage arrays and other types of storage systems are often shared by multiple host devices over a network. Applications running on the host devices each include one or more processes that perform the application functionality. The processes issue input-output (IO) operations for delivery to storage ports of the storage system. The storage ports are typically limited in number and each has limited resources for handling TO operations received from the host devices. Different ones of the host devices can run different applications with varying workloads and associated TO patterns. Such host devices also generate additional TO operations in performing various data services such as replication and migration so as to meet business continuity requirements.

Conventional host device multi-pathing arrangements are in some situations unable to deal adequately with these and other variabilities in TO processing behavior. For example, some existing multi-path layers implement a static path selection approach that does not produce optimal results in all situations. Moreover, problems can arise in these and other conventional arrangements when paths from one or more of the host devices to the storage system experience performance degradations. For example, such performance degradations can include “slow drain” issues potentially arising from imbalances in supported data rates between host devices, network switches and storage arrays.

SUMMARY

Illustrative embodiments provide path selection modification in a host device responsive to mismatch between initiator-target negotiated rates for one or more paths. The paths illustratively comprise paths through a storage area network (SAN) or other type of network over which one or more host devices communicate with at least one storage array or other type of storage system.

In some embodiments, the path selection modification is implemented in a multi-path layer that comprises at least one multi-path input-output (MPIO) driver configured to process IO operations of at least one host device that communicates with one or more storage arrays or other types of storage systems. The multi-path layer in such arrangements can be configured, for example, to modify the manner in which it performs path selection so as to provide particularly efficient load balancing in the presence of mismatch in initiator-target negotiated rates of one or more paths.

For example, the path selection modification providing efficient load balancing in an MPIO driver in some embodiments substantially reduces the likelihood that one or more paths that are adversely impacted by initiator-target negotiated rate mismatch will be selected by a load balancing algorithm or other type of path selection algorithm implemented by the MPIO driver. Accordingly, slow drain issues are alleviated, leading to improved performance in processing of IO operations.

In one embodiment, an apparatus comprises at least one processing device that includes a processor coupled to a memory. The processing device is configured to control delivery of IO operations from a host device to at least one storage system over selected ones of a plurality of paths through a network, wherein the paths are associated with respective initiator-target pairs, the initiators being implemented on the host device and the targets being implemented on the storage system. The processing device is further configured to identify one or more of the plurality of paths that each exhibits at least a threshold amount of mismatch between a negotiated rate of its initiator and a negotiated rate of its target, and to modify path selection in the host device to at least temporarily avoid selecting the one or more identified paths.

The processing device illustratively comprises at least a portion of the host device, and in some embodiments includes an MPIO driver that performs at least a portion of the identification and modification.

The initiators of the initiator-target pairs illustratively comprise respective host bus adaptors (HBAs) of the host device and the targets of the initiator-target pairs illustratively comprise respective storage array ports of the first and second storage systems. Other types of initiators and targets can be used in other embodiments.

The negotiated rates of the respective initiator and target of a particular one of the paths illustratively comprise respective negotiated data rates determined by execution of at least one link negotiation protocol for that path. For example, the initiator and the target can each separately negotiate their respective data rates with one or more switches of a switch fabric in a network connecting the initiator to the target, using a given link negotiation protocol.

Modifying path selection in the host device to at least temporarily avoid selecting the one or more identified paths illustratively comprises, for example, marking the one or more identified paths as unavailable for selection by a path selection algorithm of the host device, or otherwise marking the one or more identified paths relative to other ones of the paths in a manner that makes the one or more identified paths less likely than those other paths to be selected by a path selection algorithm of the host device.

Additional or alternative techniques can be used to at least temporarily modify path selection in the host device. For example, at least temporarily modifying path selection in the host device to avoid selecting the one or more identified paths can comprise switching or otherwise altering a path selection algorithm of the host device to change the manner in which the one or more identified paths are considered for selection relative to other ones of the paths.

In some embodiments, the path selection modification is implemented only for particular types of IO operations, illustratively read operations.

Additionally or alternatively, intentional delays may be introduced in one or more read operations as part of the modifying.

The processing device is illustratively further configured to detect for at least one of the one or more identified paths a change in the negotiated rate of at least one of its initiator and its target that causes that path to exhibit less than the threshold amount of mismatch, and responsive to the detected change, to restore the modified path selection in the host device for the at least one identified path to its state prior to the modification.

These and other illustrative embodiments include, without limitation, apparatus, systems, methods and computer program products comprising processor-readable storage media.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an information processing system configured to implement path selection modification responsive to initiator-target negotiated rate mismatch utilizing a multi-path layer of a host device in an illustrative embodiment.

FIG. 2 is a flow diagram of a process that implements path selection modification responsive to initiator-target negotiated rate mismatch utilizing a multi-path layer of a host device in an illustrative embodiment.

FIG. 3 is a block diagram showing multiple layers of a layered system architecture that includes a multi-path layer with path selection modification responsive to initiator-target negotiated rate mismatch in an illustrative embodiment.

DETAILED DESCRIPTION

Illustrative embodiments will be described herein with reference to exemplary information processing systems and associated computers, servers, storage devices and other processing devices. It is to be appreciated, however, that these and other embodiments are not restricted to the particular illustrative system and device configurations shown. Accordingly, the term “information processing system” as used herein is intended to be broadly construed, so as to encompass, for example, processing systems comprising cloud computing and storage systems, as well as other types of processing systems comprising various combinations of physical and virtual processing resources. An information processing system may therefore comprise, for example, at least one data center or other cloud-based system that includes one or more clouds hosting multiple tenants that share cloud resources. Numerous different types of enterprise computing and storage systems are also encompassed by the term “information processing system” as that term is broadly used herein.

FIG. 1 shows an information processing system 100 configured in accordance with an illustrative embodiment. The information processing system 100 comprises at least first and second host devices 102-1 and 102-2, collectively referred to herein as host devices 102. The host devices 102 are coupled to a network 104 that comprises one or more switch fabrics. The host devices 102 communicate over the network 104 via the one or more switch fabrics with at least first and second storage arrays 105-1 and 105-2, collectively referred to herein as storage arrays 105. For example, the network 104 illustratively comprises at least one storage area network (SAN) and the one or more switch fabrics illustratively comprise respective distinct switch fabrics of a set of multiple switch fabrics interconnecting the host devices 102 with the storage arrays 105 over the one or more SANs. Each of the one or more switch fabrics in some embodiments is associated with a different SAN.

The system 100 may be configured such that the first host device 102-1 communicates with the first storage array 105-1 over a first switch fabric and communicates with the second storage array 105-2 over a second switch fabric. Similarly, the second host device 102-2 can communicate with the first storage array 105-1 over the first switch fabric and communicate with the second storage array 105-2 over the second switch fabric. Numerous other interconnection arrangements are possible.

Also, other types of networks can be used in other embodiments, and references to SANs, switch fabrics or other particular network arrangements herein are for purposes of illustration only, as non-limiting examples.

Although only two host devices 102 and two storage arrays 105 are shown in the figure, this is by way of illustrative example only, and other embodiments can include additional instances of such elements. It is also possible that alternative embodiments may include only a single host device.

The host devices 102 illustratively comprise respective computers, servers or other types of processing devices configured to communicate with the storage arrays 105 over the network 104. For example, at least a subset of the host devices 102 may be implemented as respective virtual machines of a compute services platform or other type of processing platform. The host devices 102 in such an arrangement illustratively provide compute services such as execution of one or more applications on behalf of each of one or more users associated with respective ones of the host devices 102. The term “user” herein is intended to be broadly construed so as to encompass numerous arrangements of human, hardware, software or firmware entities, as well as combinations of such entities.

Compute and/or storage services may be provided for users under a Platform-as-a-Service (PaaS) model, an Infrastructure-as-a-Service (IaaS) model and/or a Function-as-a-Service (FaaS) model, although it is to be appreciated that numerous other cloud infrastructure arrangements could be used. Also, illustrative embodiments can be implemented outside of the cloud infrastructure context, as in the case of a stand-alone computing and storage system implemented within a given enterprise.

The network 104 may be implemented using multiple networks of different types to interconnect the various components of the information processing system 100. For example, the network 104 may comprise a portion of a global computer network such as the Internet, although other types of networks can be part of the network 104, including a wide area network (WAN), a local area network (LAN), a satellite network, a telephone or cable network, a cellular network, a wireless network such as a WiFi or WiMAX network, or various portions or combinations of these and other types of networks. The network 104 in some embodiments therefore comprises combinations of multiple different types of networks each comprising processing devices configured to communicate using Internet Protocol (IP) and/or other types of communication protocols.

As a more particular example, some embodiments may utilize one or more high-speed local networks in which associated processing devices communicate with one another utilizing Peripheral Component Interconnect express (PCIe) cards of those devices, and networking protocols such as InfiniBand, Gigabit Ethernet or Fibre Channel. Numerous alternative networking arrangements are possible in a given embodiment, as will be appreciated by those skilled in the art.

Although illustratively shown as separate from the network 104 in the figure, at least portions of the storage arrays 105 may be considered part of the network 104 in some embodiments. For example, in embodiments in which the network 104 comprises at least one SAN, the storage arrays 105 may be viewed as part of the one or more SANs.

The storage arrays 105-1 and 105-2 comprise respective sets of storage devices 106-1 and 106-2, collectively referred to herein as storage devices 106, coupled to respective storage controllers 108-1 and 108-2, collectively referred to herein as storage controllers 108.

The storage devices 106 of the storage arrays 105 illustratively comprise solid state drives (SSDs). Such SSDs in some embodiments are implemented using non-volatile memory (NVM) devices such as flash memory. Other types of NVM devices that can be used to implement at least a portion of the storage devices 106 include non-volatile random access memory (NVRAM), phase-change RAM (PC-RAM), magnetic RAM (MRAM), resistive RAM, spin torque transfer magneto-resistive RAM (STT-MRAM), and Intel Optane™ devices based on 3D XPoint™ memory. These and various combinations of multiple different types of storage devices may also be used. For example, hard disk drives (HDDs) can be used in combination with or in place of SSDs or other types of NVM devices.

A given storage system as the term is broadly used herein can therefore include a combination of different types of storage devices, as in the case of a multi-tier storage system comprising, for example, a memory-based fast tier and a disk-based capacity tier. In such an embodiment, each of the fast tier and the capacity tier of the multi-tier storage system comprises a plurality of storage devices with different types of storage devices being used in different ones of the storage tiers. For example, the fast tier may comprise flash drives, NVM drives or other types of SSDs while the capacity tier comprises HDDs. The particular storage devices used in a given storage tier may be varied in other embodiments, and multiple distinct storage device types may be used within a single storage tier. The term “storage device” as used herein is intended to be broadly construed, so as to encompass, for example, SSDs, HDDs, flash drives, NVM drives, hybrid drives or other types of storage devices.

In some embodiments, at least one of the storage arrays 105 illustratively comprises one or more VNX®, VMAX®, Unity™ or PowerMax™ storage arrays, commercially available from Dell EMC of Hopkinton, Mass.

As another example, one or both of the storage arrays 105 may comprise respective clustered storage systems, each including a plurality of storage nodes interconnected by one or more networks. An example of a clustered storage system of this type is an XtremIO™ storage array from Dell EMC, illustratively implemented in the form of a scale-out all-flash content addressable storage array.

A given storage system as the term is broadly used herein can additionally or alternatively comprise, for example, network-attached storage (NAS), direct-attached storage (DAS) and distributed DAS.

Other additional or alternative types of storage products that can be used in implementing a given storage system in illustrative embodiments include software-defined storage, cloud storage, object-based storage and scale-out storage. Combinations of multiple ones of these and other storage types can also be used in implementing a given storage system in an illustrative embodiment.

As mentioned above, communications between the host devices 102 and the storage arrays 105 within the system 100 may utilize PCIe connections or other types of connections implemented over one or more networks such as network 104. For example, illustrative embodiments can use interfaces such as Small Computer System Interface (SCSI), Internet SCSI (iSCSI), Serial Attached SCSI (SAS) and Serial Advanced Technology Attachment (SATA). Numerous other interfaces and associated communication protocols can be used in other embodiments.

The storage arrays 105 in some embodiments may be implemented as part of cloud infrastructure in the form of a cloud-based system such as an Amazon Web Services (AWS) system. Other examples of cloud-based systems that can be used to provide at least portions of the storage arrays 105 and possibly other portions of system 100 include Google Cloud Platform (GCP) and Microsoft Azure.

As is apparent from the foregoing, terms such as “storage array” and “storage system” as used herein are intended to be broadly construed, and a given such storage array or storage system may encompass, for example, multiple distinct instances of a commercially-available storage array.

The storage devices 106 of the storage arrays 105 are configured to store data utilized by one or more applications running on one or more of the host devices 102. The storage devices 106 on one of the storage arrays 105 are illustratively arranged in one or more storage pools. The storage arrays 105 and their corresponding storage devices 106 are examples of what are more generally referred to herein as “storage systems.” A given such storage system in the present embodiment may be shared by the host devices 102, and in such arrangements may be referred to as a “shared storage system.”

The storage devices 106 of the storage arrays 105 implement logical units (LUNs) configured to store objects for users associated with the host devices 102. These objects can comprise files, blocks or other types of objects. The host devices 102 interact with the storage arrays 105 utilizing read and write commands as well as other types of commands that are transmitted over the network 104.

Such commands in some embodiments more particularly comprise SCSI commands, although other types of commands may be used in other embodiments, including commands that are part of a standard command set, or custom commands such as a “vendor unique command” or VU command that is not part of a standard command set.

A given IO operation as that term is broadly used herein illustratively comprises one or more such commands. References herein to terms such as “input-output” and “IO” should be understood to refer to input and/or output. Thus, an IO operation relates to at least one of input and output. For example, an IO operation can comprise at least one read IO operation and/or at least one write IO operation. More particularly, IO operations may comprise write requests and/or read requests directed to a given one of the storage arrays 105.

Each IO operation is assumed to comprise one or more commands for instructing at least one of the storage arrays 105 to perform particular types of storage-related functions such as reading data from or writing data to particular logical storage volumes or other logical storage devices of one or more of the storage arrays 105. Such commands are assumed to have various payload sizes associated therewith, and the payload associated with a given command is referred to herein as its “command payload.”

A command directed by the host device 102-1 to one of the storage arrays 105 is considered an “outstanding” command until such time as its execution is completed in the viewpoint of the host device 102-1, at which time it is considered a “completed” command. The commands illustratively comprise respective SCSI commands, although other command formats can be used in other embodiments. A given such command is illustratively defined by a corresponding command descriptor block (CDB) or similar format construct. The given command can have multiple blocks of payload associated therewith, such as a particular number of 512-byte SCSI blocks or other types of blocks.

Also, the term “storage device” as broadly used herein can encompass, for example, a logical storage device such as a LUN or other logical storage volume. A logical storage device can be defined in the storage arrays 105 to include different portions of one or more physical storage devices. The storage devices 106 may therefore be viewed as comprising respective LUNs or other logical storage volumes. Logical storage devices are also referred to herein as simply “logical devices.”

Each of the host devices 102 illustratively has multiple paths to each of the storage arrays 105 via the network 104, with at least one of the storage devices 106 of one of the storage arrays 105 being visible to that host device on a given one of the paths, although numerous other arrangements are possible. A given one of the storage devices 106 may be accessible to a given host device over multiple paths. Different ones of the host devices 102 can have different numbers and types of paths to the storage arrays 105.

Different ones of the storage devices 106 of the storage arrays 105 illustratively exhibit different latencies in processing of IO operations. In some cases, the same storage device may exhibit different latencies for different ones of multiple paths over which that storage device can be accessed from a given one of the host devices 102.

The host devices 102, network 104 and storage arrays 105 in the FIG. 1 embodiment are assumed to be implemented using at least one processing platform each comprising one or more processing devices each having a processor coupled to a memory. Such processing devices can illustratively include particular arrangements of compute, storage and network resources. For example, processing devices in some embodiments are implemented at least in part utilizing virtual resources such as virtual machines (VMs) or Linux containers (LXCs), or combinations of both as in an arrangement in which Docker containers or other types of LXCs are configured to run on VMs.

Additional examples of processing platforms utilized to implement storage systems and possibly one or more associated host devices in illustrative embodiments will be described in more detail below.

The host devices 102 and the storage arrays 105 may be implemented on respective distinct processing platforms, although numerous other arrangements are possible. For example, in some embodiments at least portions of the host devices 102 and the storage arrays 105 are implemented on the same processing platform. The storage arrays 105 can therefore be implemented at least in part within at least one processing platform that implements at least a subset of the host devices 102.

The term “processing platform” as used herein is intended to be broadly construed so as to encompass, by way of illustration and without limitation, multiple sets of processing devices and associated storage systems that are configured to communicate over one or more networks. For example, distributed implementations of the host devices 102 are possible, in which certain ones of the host devices 102 reside in one data center in a first geographic location while other ones of the host devices 102 reside in one or more other data centers in one or more other geographic locations that are potentially remote from the first geographic location. Thus, it is possible in some implementations of the system 100 for different ones of the host devices 102 to reside in different data centers than the storage arrays 105. The storage arrays 105 can be similarly distributed across multiple data centers.

Although in some embodiments certain commands used by the host devices 102 to communicate with the storage arrays 105 illustratively comprise SCSI commands, other types of commands and command formats can be used in other embodiments. For example, some embodiments can implement IO operations utilizing command features and functionality associated with NVM Express (NVMe), as described in the NVMe Specification, Revision 1.3, May 2017, which is incorporated by reference herein. Other storage protocols of this type that may be utilized in illustrative embodiments disclosed herein include NVMe over Fabric, also referred to as NVMeoF, and NVMe over Transmission Control Protocol (TCP), also referred to as NVMe/TCP.

The storage arrays 105-1 and 105-2 in some embodiments may be arranged in an active-active configuration, although use of such a configuration is not required. In an example of an active-active configuration that may be used, data stored in one of the storage arrays 105 is replicated to the other one of the storage arrays 105 utilizing a replication process. Such data replication across the multiple storage arrays 105 can be used to facilitate failure recovery in the system 100. One of the storage arrays 105 may therefore operate as a production storage array relative to the other storage array which operates as a backup or recovery storage array. Examples of active-active configurations include “metro” or “stretched” high availability storage array configurations. The term “active-active configuration” as used herein is therefore intended to be broadly construed.

The storage arrays 105-1 and 105-2 may be configured to participate in a replication process, such as a synchronous replication process. In accordance with one type of synchronous replication process, a given one of the host devices 102 writes data to one of the storage arrays 105, and that host device receives an acknowledgement of success only after the data has been successfully written to both of the storage arrays 105. For example, if the host device directs a write to the first storage array 105-1, that storage array mirrors the write to the second storage array 105-2 and receives an acknowledgement of success back from the second storage array 105-2. The first storage array 105-1 then responds back to the host device with an acknowledgement of success.

The synchronous replication process is therefore configured to mirror data writes from one or more of the host devices 102 to both of the storage arrays 105. Other types of replication processes may be used in other embodiments.

For example, a “replication process” as that term is broadly used herein may include both asynchronous and synchronous replication modes as well as support for concurrent operation of such modes and separate operation of the individual modes. It is also possible in some embodiments that a given replication process implemented using storage arrays 105 may comprise only synchronous replication or only asynchronous replication, instead of multiple distinct replication modes.

It is assumed that the storage controllers 108 of the respective storage arrays 105 each comprise replication control logic and a snapshot generator. The replication control logic controls performance of the above-noted synchronous replication process. The snapshot generator is used to generate snapshots of one or more storage volumes that are subject to synchronous replication in conjunction with active-active storage clustering.

The snapshots generated by the storage controllers 108 of the storage arrays 105 illustratively comprise respective point-in-time (PIT) replicas of the storage volumes. Multiple snapshots generated over time for a given storage volume can collectively comprise a “snapshot group” and information characterizing those snapshots in some embodiments is stored in the form of a snapshot tree or other arrangement of one or more data structures suitable for storing information characterizing a snapshot group. In some embodiments, a snapshot tree for a storage volume is configured to add a new node each time a new snapshot is generated for that storage volume. The term “snapshot” as used herein is intended to be broadly construed, and in some embodiments may encompass a complete PIT replica or other types of information characterizing the state of a given storage volume at a particular time.

A given storage volume designated for synchronous replication between storage arrays 105 in the system 100 illustratively comprises a set of one or more LUNs or other storage volumes of the storage arrays 105. Each such LUN or other storage volume is assumed to comprise at least a portion of a physical storage space of one or more of the storage devices 106 of the corresponding storage arrays 105.

The host devices 102 comprise respective sets of IO queues 110-1 and 110-2, and respective MPIO drivers 112-1 and 112-2. The MPIO drivers 112 collectively comprise a multi-path layer of the host devices 102. The multi-path layer provides automated path selection functionality using respective instances of path selection logic 114-1 and 114-2 implemented within the MPIO drivers 112.

The MPIO drivers 112 may comprise, for example, otherwise conventional MPIO drivers, such as PowerPath® drivers from Dell EMC, suitably modified in the manner disclosed herein to provide functionality for path selection modification. Other types of MPIO drivers from other driver vendors may be suitably modified to incorporate functionality for path selection modification as disclosed herein.

The MPIO driver 112-1 is configured to select TO operations from its corresponding set of TO queues 110-1 for delivery to the storage arrays 105 over the network 104. The sources of the TO operations stored in the set of TO queues 110-1 illustratively include respective processes of one or more applications executing on the host device 102-1. Other types of sources of TO operations may be present in a given implementation of system 100.

The paths over which the TO operations are sent from the host device 102-1 to the storage arrays 105 illustratively comprise paths associated with respective initiator-target pairs, with each initiator comprising a host bus adaptor (HBA) or other initiating entity of the host device 102-1 and each target comprising a storage array port or other targeted entity corresponding to one or more of the storage devices 106 of the storage arrays 105. As noted above, the storage devices 106 of the storage arrays 105 illustratively comprise LUNs or other types of logical storage devices.

For example, in selecting particular ones of the paths for delivery of the TO operations to the storage arrays 105, the path selection logic 114-1 of the MPIO driver 112-1 illustratively implements a path selection algorithm that selects particular ones of the paths at least in part as a function of path information such as host device HBA and storage array port, with the path selection algorithm being configured to balance the TO operations over the paths or to achieve other load balancing or performance goals.

Selecting a particular one of multiple available paths for delivery of a selected one of the TO operations of the set of TO queues 110-1 is more generally referred to herein as “path selection.” Path selection as that term is broadly used herein can in some cases involve both selection of a particular TO operation and selection of one of multiple possible paths for accessing a corresponding logical device of one of the storage arrays 105. The corresponding logical device illustratively comprises a LUN or other logical storage volume to which the particular TO operation is directed.

A given retry of a failed IO operation under such a path selection algorithm can select a path having a different host device HBA and storage array port for a given retry than that of the path selected for the original failed IO operation.

The paths between the host devices 102 and the storage arrays 105 can change over time. For example, the addition of one or more new paths from host device 102-1 to the storage arrays 105 or the deletion of one or more existing paths from the host device 102-1 to the storage arrays 105 may result from respective addition or deletion of at least a portion of the storage devices 106 of the storage arrays 105. Addition or deletion of paths can also occur as a result of zoning and masking changes or other types of storage system reconfigurations performed by a storage administrator or other user.

In some embodiments, paths are added or deleted in conjunction with addition of a new storage array or deletion of an existing storage array from a storage system that includes multiple storage arrays, possibly in conjunction with configuration of the storage system for at least one of a migration operation and a replication operation.

In these and other situations, path discovery scans may be repeated as needed in order to discover the addition of new paths or the deletion of existing paths.

A given path discovery scan can be performed utilizing known functionality of conventional MPIO drivers, such as PowerPath® drivers.

The path discovery scan in some embodiments may be further configured to identify one or more new LUNs or other logical storage volumes associated with the one or more new paths identified in the path discovery scan. The path discovery scan may comprise, for example, one or more bus scans which are configured to discover the appearance of any new LUNs that have been added to the storage arrays 105 as well to discover the disappearance of any existing LUNs that have been deleted from the storage arrays 105.

The MPIO driver 112-1 in some embodiments comprises a user-space portion and a kernel-space portion. The kernel-space portion of the MPIO driver 112-1 may be configured to detect one or more path changes of the type mentioned above, and to instruct the user-space portion of the MPIO driver 112-1 to run a path discovery scan responsive to the detected path changes. Other divisions of functionality between the user-space portion and the kernel-space portion of the MPIO driver 112-1 are possible.

For each of one or more new paths identified in the path discovery scan, the host device 102-1 may be configured to execute a host registration operation for that path. The host registration operation for a given new path illustratively provides notification to the corresponding one of the storage arrays 105 that the host device 102-1 has discovered the new path.

As is apparent from the foregoing, MPIO driver 112-1 of host device 102-1 is configured to control delivery of IO operations from the host device 102-1 to the first and second storage arrays 105 over selected paths through the network 104.

Other host device components can additionally or alternatively perform at least portions of controlling delivery of IO operations over selected paths, such as one or more host device processors or other control logic instances. Illustrative embodiments are therefore not limited to arrangements in which MPIO drivers perform such delivery control functions for IO operations. Moreover, terms such as “controlling delivery” of an IO operation as used herein are intended to be broadly construed so as to encompass, for example, selecting from a plurality of paths a particular path over which a particular IO operation is to be sent to one of the storage arrays 105, and sending the IO operation over that path.

The MPIO driver 112-1 in implementing at least portions of path selection modification functionality of host device 102-1 is further configured in illustrative embodiments to identify one or more of the plurality of paths that each exhibits at least a threshold amount of mismatch between a negotiated rate of its initiator and a negotiated rate of its target, and to modify path selection in the host device 102-1 to at least temporarily avoid selecting the one or more identified paths. For example, modifying path selection in the host device 102-1 to at least temporarily avoid selecting the one or more identified paths illustratively comprises modifying the path selection performed by path selection logic 114-1 for a particular one of the one or more identified paths for at least a portion of a time period during which its corresponding at least threshold amount of mismatch exists.

The modification of the path selection in the host device 102-1 in some embodiments is implemented only for certain types of IO operations, illustratively read operations. Additionally or alternatively, intentional delays may be introduced by the MPIO driver 112-1 in one or more read operations as part of the modifying.

Accordingly, in some embodiments modifying path selection illustratively comprises diverting read operations to paths that are not exhibiting at least threshold amounts of mismatch between their respective initiator and target negotiated rates. The read operations are therefore illustratively diverted away from paths that are currently experiencing slow drain issues of the type described herein. Instead of or in addition to such diversion of read operations, the MPIO driver 112-1 can slow the rate at which read operations are sent, in order to allow the host device 102-1 additional time to consume read data sent by the storage array 105 and to reduce congestion on the switches of the one or more switch fabrics of the network 104. Combinations of such techniques can also be used.

Therefore, some embodiments both divert read operations and slow the rate of read operations, while other embodiments only divert the read operations or only slow the rate at which the read operations are sent. Numerous other arrangements involving path selection modification responsive to detected mismatch can be used.

In some embodiments, the negotiated rates of the respective initiator and target of a particular one of the paths comprise respective negotiated data rates determined by execution of at least one link negotiation protocol for that path. The link negotiation protocol is illustratively performed separately by the initiator and the target, and involves each such component separately interacting with at least one switch of a switch fabric of the network 104 in order to determine the negotiated rate. The term “negotiated rate” therefore illustratively comprises a rate negotiated between an initiator or a target and a switch of a switch fabric of network 104. However, the term “negotiated rate” as used herein is intended to be broadly construed so as to also encompass, for example, arrangements that refer to negotiated speeds. Any of a wide variety of different link negotiation protocols can be used, including auto-negotiation protocols, as will be readily appreciated by those skilled in the art.

For example, some embodiments are configured to utilize link negotiation protocols that allow negotiation of data rates such as 1G, 2G, 4G, 8G, 16G, 32G etc. where G denotes Gigabits per second (Gb/sec). The link bandwidth is illustratively specified in terms of Megabytes per second (MB/sec), and the actual amount of data that can be sent over the link in practice is typically somewhat lower than the negotiated data rate. Accordingly, a negotiated rate of 1G in some systems may correspond to an actual achievable data rate that is lower than 100 MB/sec, such as a rate of 85 MB/sec.

The term “negotiated rate” as used herein is therefore intended to be broadly construed, so as to encompass, for example, a theoretical negotiated rate or an actual achievable data rate that corresponds to the theoretical negotiated rate within a given system.

It is also to be appreciated that a wide variety of other types of rate negotiation may be performed in other embodiments.

As indicated previously, problems can arise in conventional systems due to slow drain issues arising from imbalances in supported data rates between host devices, network switches and storage arrays. Illustrative embodiments herein overcome those problems by detecting paths that are exhibiting substantial initiator-target mismatch, and modifying path selection to at least temporarily avoid selecting those paths. Accordingly, some embodiments are configured to detect conditions that tend to give rise to slow drain issues, and to proactively adjust path selection in a manner that prevents or otherwise alleviates the slow drain issues and their adverse impacts on IO processing performance. For example, efficient load balancing can be provided by the path selection logic 114-1 in the presence of mismatch in initiator-target negotiated rates of one or more paths. Such arrangements can substantially reduce the likelihood that one or more paths that are adversely impacted by initiator-target negotiated rate mismatch will be selected by a load balancing algorithm or other type of path selection algorithm implemented by the path selection logic 114-1. As a result, slow drain issues are alleviated, leading to improved performance in processing of IO operations.

The MPIO driver 112-1 can determine negotiated rates of the targets of respective ones of the paths by communicating with one or more of the storage arrays 105. For example, the storage arrays 105 may be configured to report such information for each of their ports to the host device 102-1. The MPIO driver 112-1 can determine negotiated rates of the initiators of respective ones of the paths from one or more data structures maintained by an operating system of the host device 102-1. Additionally or alternatively, the MPIO driver 112-1 can determine negotiated rates of the initiators of respective ones of the paths by communicating with one or more of the storage arrays 105. For example, the storage arrays 105 may be configured to detect and report such information to the host device 102-1 for any HBAs in communication with their ports.

Thus, in embodiments in which the storage arrays 105 include functionality for exporting negotiated rates of their targets, and possibly also negotiated rates of initiators that are in communication with those targets, the MPIO driver 112-1 can make use of such exporting functionality to determine at least a subset of the negotiated rates. Other techniques can be used by the MPIO driver 112-1 or host device 102-1 to determine negotiated rates for initiators and targets of respective paths in other embodiments.

The mismatch detected by the MPIO driver 112-1 in some embodiments is a mismatch in which the negotiated rate of the target of a given path is at least the threshold amount higher than the negotiated rate of its initiator. Accordingly, an at least threshold amount of mismatch in such embodiments is a mismatch in which the target negotiated rate exceeds the initiator negotiated rate by at least the threshold amount, which would tend to indicate that the storage array port can supply read data to a network switch significantly faster than the corresponding HBA of the host device 102-1 can consume that read data from the network switch, leading to a slow drain issue. The threshold can vary depending upon the particular system implementation and can take into account factors such as the susceptibility of the system to slow drain issues, possibly based at least in part on stored information characterizing previous slow drain issues in the system. Other types of mismatches in initiator-target negotiated rates can be detected using other types of thresholds in other embodiments. Terms such as “threshold” and “threshold amount” as used herein are therefore intended to be broadly construed.

It should be noted that there may be situations in which there is a substantial mismatch between the initiator and target negotiated rates for a given path, but the host device 102-1 is generating very few read operations relative to the available link bandwidth, and therefore such mismatch may not lead to a slow drain issue. For example, if an HBA of host device 102-1 has negotiated a relatively low rate with a network switch for a given path, such as a 1G rate, and a corresponding storage array port of that path has negotiated a relatively high rate with a network switch, such as a 4G rate, there is illustratively at least a threshold amount of mismatch between the initiator and target negotiated rates for the path, with the target in this case having a substantially higher negotiated rate than the initiator. However, if the host device 102-1 is generating very few reads, or only generating reads for very small amounts of data, such as one read operation per second for a single block, this detected mismatch is not necessarily problematic. Accordingly, the MPIO driver 112-1 can take these and other dynamic factors into account in its path selection modification decisions. This example indicates that not all detected mismatches necessarily lead to path selection modification. Instead, the MPIO driver 112-1 can detect multiple mismatches, and prioritize certain ones of the detected mismatches, such as those that are expected to have a greater adverse impact on IO processing performance, for implementation of corresponding path selection modification.

In some embodiments, the MPIO driver 112-1 or another component of the host device 102-1 is configured to generate at least one notification for delivery to a user of the system 100, responsive to identifying one or more of the plurality of paths that each exhibits at least a threshold amount of mismatch between a negotiated rate of its initiator and a negotiated rate of its target. For example, such notifications can be sent to a host administrator of the host devices 102, a storage administrator of the storage arrays 105, users of applications running on the host devices 102, and/or one more other users of the system 100. Separate notifications can be sent for each identified path, or a single notification can be sent that specifies multiple identified paths each having at least the threshold amount of mismatch.

Although in the present embodiment and other embodiments herein, MPIO drivers are used to perform path selection modification in conjunction with mismatches in initiator-target negotiated rates, this is by way of illustrative example only, and other host device components can alternatively implement at least portions of such path selection modification functionality. Accordingly, path selection modification functionality in some embodiments can be distributed across multiple host device components, possibly including MPIO drivers in combination with other host device components such as host device processors and associated control logic instances.

As described above, the MPIO driver 112-1 in the FIG. 1 embodiment is configured to detect at or above threshold mismatches in initiator-target negotiated rates for respective paths between the host device 102-1 and the storage arrays 105. The MPIO driver 112-1 illustratively maintains one or more data structures that specify each path or set of paths associated with a given logical storage device to which IO operations may be directed by the MPIO driver 112-1, including information characterizing the particular HBA and storage array port that are the respective initiator and target for each such path.

The above-noted data structures may more particularly comprise storage array objects that include “inventories” of storage devices of their corresponding storage arrays, with such objects being maintained by the MPIO driver 112-1. For example, a first data structure illustratively comprises a first object specifying a first set of paths between the host device 102-1 and at least one of the first and second storage arrays 105, and a second data structure comprises a second object specifying a second set of paths between the host device 102-1 and at least one of the first and second storage arrays 105. In some embodiments, at least one of the first object and the second object comprises a federated object that specifies paths to both the first and the second storage arrays for a paired logical device that is identified by the MPIO driver 112-1 as a single logical device but has separate corresponding logical devices on the respective first and second storage arrays 105.

Other types and arrangements of data structures maintained by the MPIO driver 112-1 can be used in identifying paths that are exhibiting at or above threshold mismatches in initiator-target negotiated rates.

In some embodiments, the MPIO driver 112-1 in modifying path selection in the host device 102-1 to at least temporarily avoid selecting the one or more identified paths is more particularly configured, for example, to mark the one or more identified paths as unavailable for selection by a path selection algorithm implemented by the path selection logic 114-1.

As another example, the MPIO driver 112-1 in modifying path selection in the host device 102-1 to at least temporarily avoid selecting the one or more identified paths is more particularly configured to weight the one or more identified paths relative to other ones of the paths in a manner that makes the one or more identified paths less likely than those other paths to be selected by a path selection algorithm implemented by the path selection logic 114-1. More particularly, relatively high weights could be assigned to the one or more identified paths in the context of a path selection algorithm that gives priority in path selection to paths having relatively low weights, or vice versa.

In arrangements of this type, modifying path selection in the host device to at least temporarily avoid selecting the one or more identified paths comprises marking the one or more identified paths relative to other ones of the paths in a manner that makes the one or more identified paths less likely than those other paths to be selected by a path selection algorithm implemented by the path selection logic 114-1.

Additionally or alternatively, modifying path selection in the host device 102-1 to at least temporarily avoid selecting the one or more identified paths can comprise altering a load balancing algorithm or other path selection algorithm of the path selection logic 114-1 to change the manner in which the one or more identified paths are considered for selection relative to other ones of the paths. For example, the MPIO driver 112-1 can illustratively modify the operation of a load balancing algorithm that it uses in path selection in the path selection logic 114-1 based at least in part on the one or more identified paths that have at or above threshold mismatches in their initiator-target negotiated rates.

The MPIO driver 112-1 can also detect for at least one of the one or more identified paths a change in the negotiated rate of at least one of its initiator and its target that causes that path to exhibit less than the threshold amount of mismatch, and responsive to the detected change, to restore the modified path selection in the host device 102-1 for that path or paths to its state prior to the modification. Accordingly, by way of illustrative example, after all of the paths previously identified as exhibiting at least threshold amounts of mismatch in their initiator-target negotiated rates no longer exhibit that at or above threshold mismatch, any corresponding modifications in path selection implemented by the MPIO driver 112-1 can be reversed, to thereby restore normal path selection functionality.

The above-described functions associated with path selection modification in the MPIO driver 112-1 are illustratively carried out at least in part under the control of its path selection logic 114-1. For example, the path selection logic 114-1 is illustratively configured to control performance of the steps of the flow diagram to be described below in conjunction with FIG. 2. In other embodiments, the FIG. 2 process can be performed at least in part by other host device components, such as by one or more host device processors and/or associated control logic instances.

It is assumed that the other MPIO driver 112-2 is configured in a manner similar to that described above and elsewhere herein for the first MPIO driver 112-1. The MPIO driver 112-2 is therefore similarly configured to select IO operations from its corresponding one of the sets of IO queues 110 for delivery to the storage arrays 105 over the network 104 and to perform the disclosed path selection modification functionality. Accordingly, path selection modification functionality described above in the context of the first MPIO driver 112-1 is assumed to be similarly performed by the other MPIO driver 112-2.

The MPIO drivers 112 in some embodiments can include well-known MPIO functionality such as that described in “Dell EMC SC Series Storage and Microsoft Multipath I/O,” Dell EMC, CML1004, July 2018, which is incorporated by reference herein. Such conventional MPIO functionality is suitably modified in illustrative embodiments disclosed herein to support path selection modification.

It is to be appreciated that the above-described features of system 100 and other features of other illustrative embodiments are presented by way of example only, and should not be construed as limiting in any way. Accordingly, different numbers, types and arrangements of system components such as host devices 102, network 104, storage arrays 105, storage devices 106, sets of IO queues 110, MPIO drivers 112 and instances of path selection logic 114 can be used in other embodiments.

It should also be understood that the particular sets of modules and other components implemented in the system 100 as illustrated in FIG. 1 are presented by way of example only. In other embodiments, only subsets of these components, or additional or alternative sets of components, may be used, and such components may exhibit alternative functionality and configurations.

The operation of the information processing system 100 will now be described in further detail with reference to the flow diagram of the illustrative embodiment of FIG. 2. The process as shown includes steps 200 through 208, and is suitable for use in the system 100 but is more generally applicable to other types of systems comprising one or more host devices and at least one storage system. The storage system in this embodiment is assumed to more particularly comprise a storage array comprising a plurality of storage devices. The storage devices of the storage array are assumed to include logical storage devices such as LUNs or other logical storage volumes.

The steps of the FIG. 2 process are illustratively performed primarily by or under the control of an MPIO driver of a given host device, such as the MPIO driver 112-1 of the first host device 102-1 of system 100, although other arrangements of system components can perform at least portions of one or more of the steps in other embodiments. The functionality of the FIG. 2 process is illustratively performed in conjunction with a load balancing algorithm or other path selection algorithm executed by the path selection logic 114-1.

In step 200, the MPIO driver performs path selection while monitoring for one or more paths each having at least a threshold amount of mismatch between its initiator and target negotiated rates.

In step 202, a determination is made by the MPIO driver as to whether or not one or more paths each having at least a threshold amount of mismatch have been detected. If at least one such path has been detected, the process moves to step 204, and otherwise returns to step 200 to continue performing path selection while monitoring for one or more paths each having at least a threshold amount of mismatch between its initiator and target negotiated rates.

In step 204, which is reached responsive to detection of at least one path having at least the threshold amount of mismatch between its initiator and target negotiated rates, the MPIO driver uses modified path selection that at least temporarily avoids selecting the one or more identified paths. Although not explicitly indicated in step 204, the MPIO driver also monitors for cessation of the previously-detected mismatch in initiator-target negotiated rates of the one or more identified paths. In some embodiments, selection of the one or more identified paths is avoided for at least portions of a period of time for which the detected mismatch continues to exist for each such identified path. These and other arrangements are considered to be encompassed by the term “at least temporarily avoid” as broadly used herein.

In step 206, a determination is made by the MPIO driver as to whether or not the one or more identified paths no longer exhibit at least the threshold amount of mismatch. If the one or more identified paths no longer exhibit at least the threshold amount of mismatch, the process moves to step 208, and otherwise returns to step 204 to continue using the modified path selection that avoids selecting the one or more identified paths, while also monitoring for cessation of the previously-detected mismatch in initiator-target negotiated rates of the one or more identified paths.

In step 208, which is reached responsive to detection of the one or more identified paths no longer exhibiting at least the threshold amount of mismatch in initiator-target negotiated rates, the MPIO driver restores the modified path selection to its state prior to the modification. The process then returns to step 200 as indicated.

The various steps of the FIG. 2 process are illustratively shown as being performed serially, but certain steps can at least partially overlap with other steps.

Also, multiple additional instances of the FIG. 2 process can be performed in respective ones of one or more additional host devices that share at least one storage array or other storage system.

As another example, different instances of the FIG. 2 process can be performed for each of a plurality of different paths, with each such instance separately detecting mismatch in an initiator-target negotiated rate for its corresponding path and controlling path selection with respect to that path.

The particular processing operations and other system functionality described in conjunction with the flow diagram of FIG. 2 are presented by way of illustrative example only, and should not be construed as limiting the scope of the disclosure in any way. Alternative embodiments can use other types of processing operations involving host devices, storage systems and path selection modification functionality. For example, the ordering of the process steps may be varied in other embodiments, or certain steps may be performed at least in part concurrently with one another rather than serially. Also, one or more of the process steps may be repeated periodically, or multiple instances of the process can be performed in parallel with one another in order to implement a plurality of different path selection modification arrangements within a given information processing system.

Functionality such as that described in conjunction with the flow diagram of FIG. 2 can be implemented at least in part in the form of one or more software programs stored in memory and executed by a processor of a processing device such as a computer or server. As will be described below, a memory or other storage device having executable program code of one or more software programs embodied therein is an example of what is more generally referred to herein as a “processor-readable storage medium.”

Referring now to FIG. 3, another illustrative embodiment is shown. In this embodiment, an information processing system 300 comprises application processes 311, path selection logic 314 and replication control logic 321. The system 300 is configured in accordance with a layered system architecture that illustratively includes a host device processor layer 330, an MPIO layer 332, an HBA layer 334, a switch fabric layer 336, a storage array port layer 338 and a storage array processor layer 340. As illustrated in the figure, the host device processor layer 330, the MPIO layer 332 and the HBA layer 334 are associated with one or more host devices, the switch fabric layer 336 is associated with one or more SANs or other types of networks, and the storage array port layer 338 and storage array processor layer 340 are associated with one or more storage arrays (“SAs”).

The system 300 in this embodiment implements path selection modification in conjunction with detection of at least threshold amounts of mismatch in initiator-target negotiated rates for one or more paths, in a manner similar to that described elsewhere herein. The application processes 311 are illustratively running in one or more host device processors of the host device processor layer 330. The path selection modification functionality in this embodiment is assumed to be controlled at least in part by path selection logic 314 of the MPIO layer 332, although other arrangements are possible.

The MPIO layer 332 is an example of what is also referred to herein as a multi-path layer, and comprises one or more MPIO drivers implemented in respective host devices. Each such MPIO driver illustratively comprises an instance of path selection logic 314 configured to implement functionality for path selection modification in conjunction with detection of at least threshold amounts of mismatch in initiator-target negotiated rates for one or more paths as previously described. Additional or alternative layers and path selection logic arrangements can be used in other embodiments.

The replication control logic 321 implemented in the storage array processor layer 340 controls the active-active configuration of a given pair of storage arrays, or other types of replication arrangements implemented in the system 300. For example, the replication control logic 321 can include functionality for carrying out a synchronous replication process between first and second storage arrays in the active-active configuration. It is also possible in some embodiments that the replication control logic 321 can include multiple distinct replication control logic instances for respective ones of a plurality of storage arrays of the system 300. Although not explicitly shown in the figure, additional replication control logic is illustratively implemented in the host device processor layer 330, or elsewhere in the system 300, such as in the MPIO layer 332.

In the system 300, path selection logic 314 is configured to select different paths for sending IO operations from a given host device to a storage array. These paths as illustrated in the figure include a first path from a particular HBA denoted HBA1 through a particular switch fabric denoted SF1 to a particular storage array port denoted PORT1, and a second path from another particular HBA denoted HBA2 through another particular switch fabric denoted SF2 to another particular storage array port denoted PORT2.

These two particular paths are shown by way of illustrative example only, and in many practical implementations there will typically be a much larger number of paths between the one or more host devices and the one or more storage arrays, depending upon the specific system configuration and its deployed numbers of HBAs, switch fabrics and storage array ports. For example, each host device in the FIG. 3 embodiment can illustratively have a set of n paths to a shared storage array, or alternatively different ones of the host devices can have different numbers and types of paths to the storage array.

The path selection logic 314 of the MPIO layer 332 in this embodiment therefore selects paths for delivery of IO operations to the one or more storage arrays having the storage array ports of the storage array port layer 338. In selecting the paths in conjunction with detected mismatch, the path selection logic 314 ensures that such paths are selected from a limited set of paths, namely, a set of paths that excludes those paths that are identified as being adversely impacted by detected mismatch, as described elsewhere herein. For example, the path selection logic 314 can limit a load balancing algorithm or other path selection algorithm normally used to select the paths for delivery of IO operations such that it considers only paths other than those paths that are identified as exhibiting at least threshold amounts of mismatch in their initiator-target negotiated rates. This can be achieved, for example, by adjusting weights applied to the identified paths, or through other path selection modifications.

Accordingly, in this embodiment the host devices of system 300 through their respective MPIO drivers and respective instances of path selection logic 314 provide functionality for path selection modification in conjunction with detection of at least threshold amounts of mismatch in initiator-target negotiated rates, possibly with involvement of other host device or system components.

Some implementations of the system 300 can include a relatively large number of host devices (e.g., 1000 or more host devices), although as indicated previously different numbers of host devices, and possibly only a single host device, may be present in other embodiments. Each of the host devices is typically allocated with a sufficient number of HBAs to accommodate predicted performance needs. In some cases, the number of HBAs per host device is on the order of 4, 8 or 16 HBAs, although other numbers of HBAs could be allocated to each host device depending upon the predicted performance needs. A typical storage array may include on the order of 128 ports, although again other numbers can be used based on the particular needs of the implementation. The number of host devices per storage array port in some cases can be on the order of 10 host devices per port. The HBAs of the host devices are assumed to be zoned and masked to the storage array ports in accordance with the predicted performance needs, including user load predictions.

A given host device of system 300 can be configured to initiate an automated path discovery process to discover new paths responsive to updated zoning and masking or other types of storage system reconfigurations performed by a storage administrator or other user. For certain types of host devices, such as host devices using particular operating systems such as Windows, ESX or Linux, automated path discovery via the MPIO drivers of a multi-path layer is typically supported. Other types of host devices using other operating systems such as AIX in some implementations do not necessarily support such automated path discovery, in which case alternative techniques can be used to discover paths.

Again, different instances of the above-described path selection modification process can be performed by different MPIO drivers in different host devices.

Another example of a path selection modification process implemented utilizing a multi-path layer such as MPIO layer 332 of the FIG. 3 embodiment will now be described in more detail. Such a process utilizes path selection logic of one or more host devices to provide modified path selection responsive to detected mismatch in initiator-target negotiated rates.

As indicated previously, slow drain issues and other problems can arise when there is a mismatch in negotiated rates between an initiator and a target of a given path from a host device to a storage array or other storage system. For example, path selection logic in conventional host device implementations would generally continue to select such paths, potentially leading to degraded 10 processing performance.

Illustrative embodiments disclosed herein advantageously overcome these and other drawbacks of conventional arrangements, for example, though path selection modification in a multi-path layer of the host device, as will now be further described in the context of the present example.

A mismatch in initiator-target negotiated rates in some embodiments is one in which a rate negotiated by an HBA with a network switch is substantially lower than a rate negotiated by a corresponding storage array port with a network switch, potentially leading to a slow drain issue within the system. The issue typically presents itself in the context of a read command, where the host device sends a read command for a certain payload. The storage array retrieves the data from the appropriate storage device(s) and sends it to the host device over the path. If the storage array negotiated rate for the storage array port of the path is substantially higher than the host device negotiated rate for the HBA of the path, the storage array will send data to the network switch faster than the host device can read from the network switch, and a backlog of data from the storage array will accumulate in the network switch.

This backlog can consume network switch IO buffers normally used for temporary storage of data in the event of short-term minor speed gradients. When the network switch lacks sufficient available IO buffers, other communication between the host device and the storage array can slow down considerably.

The slow drain issue typically does not manifest itself in write commands. This is generally due to various flow control mechanisms that are commonly performed in conjunction with write commands, such as those implemented utilizing TRANSFER RDY messages of standard storage protocols.

Slow drain issues can also arise when a new storage array is introduced into an existing environment, as in the case of seamless migration from a first storage array to a second storage array, where the second storage array supports higher storage array port data rates than the first storage array. In this context, a slow drain issue can arise when the host device switches over from use of the first storage array to use of the second storage array after the migration is complete. Slow drain issues can also occur when a storage array port goes bad and is replaced by new storage array port hardware that supports a higher data rate.

These and other issues are addressed in the present example by a path selection modification process, as will now be described in more detail. The process in the present example comprises an algorithm performed by a multi-path layer of a host device and includes the following steps:

1. An MPIO driver communicates with a storage array that exports information specifying negotiated rates of its ports.

2. The MPIO driver obtains negotiated rates of respective HBAs of its corresponding host device from the host device operating system or from the storage array if the storage array detects the HBA negotiated rates and exports them to the MPIO driver.

3. The MPIO driver utilizes the information that it obtained in Steps 1 and 2 regarding the negotiated rates of the storage array ports and the negotiated rates of the HBAs to identify at least threshold amounts of mismatch between initiator and target negotiated rates for each of one or more paths.

4. The MPIO driver generates one or more notifications regarding potential slow drain issues based on the detected mismatches and sends those notifications to one or more system users, such as host administrators or storage administrators.

5. The MPIO driver performs path selection modification by avoiding selection of the paths having at least threshold amounts of mismatch for sending read operations from the host device to the storage arrays. For example, the MPIO driver illustratively schedules read operations on only those paths that are not experiencing such mismatch between their initiator and target negotiated rates, so as to avoid selecting paths that are susceptible to slow drain issues for the read operations.

6. If all or most paths have at least threshold amounts of mismatch between their respective initiator and target negotiated rates, the MPIO driver introduces delays between read operations so as to ensure that the host device through such read operations is not requesting more read payload that it can consume. For example, when a read operation is sent to a storage array port on a path for which the storage array port negotiated speed is at or above the threshold amount higher than the HBA negotiated rate, a temporary slow drain issue might arise when the storage array sends data at a rate faster than the HBA can consume it, leading to creation of a data backlog on a network switch. However, the MPIO driver in this and other similar situations can delay sending additional read operations for a period of time that will enable one or more network switches to service other IO operations, which may have been impacted by the temporary lack of available IO buffers in the one or more network switches. Such an arrangement advantageously limits the impact of the slow drain issue on other IO operations.

7. The MPIO driver continues to monitor the initiator-target negotiated rates for respective paths and continues to adjust its path selection in a dynamic manner to reduce exposure of the system to the adverse impacts of slow drain issues.

These particular steps are illustrative only, and additional or alternative steps can be used in other embodiments. Also, although shown as being performed serially, one or more of the steps may each at least partially overlap with other ones of the steps.

Illustrative embodiments can be implemented, for example, in one or more MPIO drivers of one or more host devices, with such MPIO drivers collectively providing a multi-path layer of the host devices.

For example, some embodiments are implemented though modification of otherwise conventional multi-pathing software, such as PowerPath® drivers commercially available from Dell EMC. Other embodiments can be implemented in other MPIO drivers from other multi-pathing software vendors.

Moreover, other host device components, such as logic instances and/or host processors, can additionally or alternatively be used.

The process in the present example advantageously provides proactive adjustments in a path selection algorithm responsive to detection of at least threshold amounts of mismatch in initiator-target negotiated rates for respective paths, in a manner that improves overall IO processing performance.

The process is illustratively performed by one or more MPIO drivers and associated path selection logic instances of a multi-path layer of a given host device. A similar process is assumed to be performed on any respective other host devices.

Other types of path selection modification involving alteration of load balancing logic or other path selection logic can be implemented in one or more host devices in other embodiments in conjunction with detected mismatch in initiator-target negotiated rates for one or more paths to a storage array or other storage system.

Some embodiments include only a single host device, although multiple host devices are used in illustrative embodiments. For example, a single host device can be connected to two storage arrays that are arranged in an active-active configuration.

Also, it should be noted that the host devices in a given embodiment need not be in an active-active configuration. For example, multiple host devices can be arranged in a cluster and the host devices can be arranged in active-passive configurations, active-active configurations, or combinations thereof.

The particular path selection modification arrangements described above are presented by way of illustrative example only. Numerous alternative arrangements of these and other features can be used in implementing path selection modification in other embodiments.

The illustrative embodiments disclosed herein can provide a number of significant advantages relative to conventional arrangements. For example, some embodiments configure a host device to include path selection modification functionality for paths utilized to communicate with one or more storage systems, such as first and second storage systems arranged in an active-active configuration.

Such embodiments are advantageously configured to provide path selection modification in conjunction with detection of at least threshold amounts of mismatch between initiator and target negotiated rates for one or more paths. As a result, more efficient load balancing is provided in the presence of the detected mismatch.

For example, the path selection modification provided by an MPIO driver or other host device component or set of components in some embodiments substantially reduces the likelihood that one or more paths that are adversely impacted by mismatch in initiator-target negotiated rates will be selected by a load balancing algorithm or other type of path selection algorithm implemented by the MPIO driver.

Accordingly, slow drain issues are prevented or otherwise alleviated, leading to improved performance in processing of IO operations.

These and other illustrative embodiments are much more efficient and effective than conventional approaches that swap hardware or manually use storage array resources to tell the storage array to lower its bandwidth when communicating with a specific slower initiator of a given path.

The disclosed functionality can be implemented using a wide variety of types of host devices each configured to interact with one or more different storage arrays or other types of storage systems.

These and other arrangements are advantageously configured to provide path selection modification for efficient load balancing even in the presence of substantial path changes such as those that may result when paths are added or deleted as a result of zoning and masking changes or other types of storage system reconfigurations performed by a storage administrator or other user.

It is to be appreciated that the particular advantages described above are associated with particular illustrative embodiments and need not be present in other embodiments. Also, the particular types of information processing system features and functionality as illustrated in the drawings and described above are exemplary only, and numerous other arrangements may be used in other embodiments.

It was noted above that portions of an information processing system as disclosed herein may be implemented using one or more processing platforms. Illustrative embodiments of such platforms will now be described in greater detail. These and other processing platforms may be used to implement at least portions of other information processing systems in other embodiments. A given such processing platform comprises at least one processing device comprising a processor coupled to a memory.

One illustrative embodiment of a processing platform that may be used to implement at least a portion of an information processing system comprises cloud infrastructure including virtual machines implemented using a hypervisor that runs on physical infrastructure. The cloud infrastructure further comprises sets of applications running on respective ones of the virtual machines under the control of the hypervisor. It is also possible to use multiple hypervisors each providing a set of virtual machines using at least one underlying physical machine. Different sets of virtual machines provided by one or more hypervisors may be utilized in configuring multiple instances of various components of the system.

These and other types of cloud infrastructure can be used to provide what is also referred to herein as a multi-tenant environment. One or more system components such as virtual machines, or portions thereof, are illustratively implemented for use by tenants of such a multi-tenant environment.

Cloud infrastructure as disclosed herein can include cloud-based systems such as AWS, GCP and Microsoft Azure. Virtual machines provided in such systems can be used to implement a fast tier or other front-end tier of a multi-tier storage system in illustrative embodiments. A capacity tier or other back-end tier of such a multi-tier storage system can be implemented using one or more object stores such as Amazon S3, GCP Cloud Storage, and Microsoft Azure Blob Storage.

In some embodiments, the cloud infrastructure additionally or alternatively comprises a plurality of containers illustratively implemented using respective operating system kernel control groups of one or more container host devices. For example, a given container of cloud infrastructure illustratively comprises a Docker container or other type of LXC implemented using a kernel control group. The containers may run on virtual machines in a multi-tenant environment, although other arrangements are possible. The containers may be utilized to implement a variety of different types of functionality within the system 100. For example, containers can be used to implement respective compute nodes or storage nodes of a cloud-based system. Again, containers may be used in combination with other virtualization infrastructure such as virtual machines implemented using a hypervisor.

Another illustrative embodiment of a processing platform that may be used to implement at least a portion of an information processing system comprises a plurality of processing devices which communicate with one another over at least one network. The network may comprise any type of network, including by way of example a global computer network such as the Internet, a WAN, a LAN, a satellite network, a telephone or cable network, a cellular network, a wireless network such as a WiFi or WiMAX network, or various portions or combinations of these and other types of networks.

Each processing device of the processing platform comprises a processor coupled to a memory. The processor may comprise a microprocessor, a microcontroller, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a graphics processing unit (GPU) or other type of processing circuitry, as well as portions or combinations of such circuitry elements. The memory may comprise random access memory (RAM), read-only memory (ROM), flash memory or other types of memory, in any combination. The memory and other memories disclosed herein should be viewed as illustrative examples of what are more generally referred to as “processor-readable storage media” storing executable program code of one or more software programs.

Articles of manufacture comprising such processor-readable storage media are considered illustrative embodiments. A given such article of manufacture may comprise, for example, a storage array, a storage disk or an integrated circuit containing RAM, ROM, flash memory or other electronic memory, or any of a wide variety of other types of computer program products. The term “article of manufacture” as used herein should be understood to exclude transitory, propagating signals.

Also included in the processing device is network interface circuitry, which is used to interface the processing device with the network and other system components, and may comprise conventional transceivers.

As another example, portions of a given processing platform in some embodiments can comprise converged infrastructure such as VxRail™, VxRack™, VxRack™ FLEX, VxBlock™ or Vblock® converged infrastructure from Dell EMC.

Again, these particular processing platforms are presented by way of example only, and other embodiments may include additional or alternative processing platforms, as well as numerous distinct processing platforms in any combination, with each such platform comprising one or more computers, servers, storage devices or other processing devices.

It should therefore be understood that in other embodiments different arrangements of additional or alternative elements may be used. At least a subset of these elements may be collectively implemented on a common processing platform, or each such element may be implemented on a separate processing platform.

Also, numerous other arrangements of computers, servers, storage devices or other components are possible in an information processing system as disclosed herein. Such components can communicate with other elements of the information processing system over any type of network or other communication media.

As indicated previously, components of an information processing system as disclosed herein can be implemented at least in part in the form of one or more software programs stored in memory and executed by a processor of a processing device. For example, at least portions of the functionality of host devices 102, network 104 and storage arrays 105 are illustratively implemented in the form of software running on one or more processing devices. As a more particular example, the instances of path selection logic 114 may be implemented at least in part in software, as indicated previously herein.

It should again be emphasized that the above-described embodiments are presented for purposes of illustration only. Many variations and other alternative embodiments may be used. For example, the disclosed techniques are applicable to a wide variety of other types of information processing systems, utilizing other arrangements of host devices, networks, storage systems, storage arrays, storage devices, processors, memories, IO queues, MPIO drivers, path selection logic and additional or alternative components. Also, the particular configurations of system and device elements and associated processing operations illustratively shown in the drawings can be varied in other embodiments. For example, a wide variety of different MPIO driver configurations and associated path selection modification arrangements can be used in other embodiments. Moreover, the various assumptions made above in the course of describing the illustrative embodiments should also be viewed as exemplary rather than as requirements or limitations. Numerous other alternative embodiments within the scope of the appended claims will be readily apparent to those skilled in the art. 

What is claimed is:
 1. An apparatus comprising: at least one processing device comprising a processor coupled to a memory; said at least one processing device being configured: to control delivery of input-output operations from a host device to at least one storage system over selected ones of a plurality of paths through a network, wherein the paths are associated with respective initiator-target pairs, the initiators being implemented on the host device and the targets being implemented on said at least one storage system; to identify one or more of the plurality of paths that each exhibits at least a threshold amount of mismatch between a negotiated rate of its initiator and a negotiated rate of its target; and to modify path selection in the host device to at least temporarily avoid selecting the one or more identified paths.
 2. The apparatus of claim 1 wherein modifying path selection in the host device to at least temporarily avoid selecting the one or more identified paths comprises modifying the path selection for a particular one of the one or more identified paths for at least a portion of a time period during which its corresponding at least threshold amount of mismatch exists.
 3. The apparatus of claim 1 wherein the negotiated rates of the respective initiator and target of a particular one of the paths comprise respective negotiated data rates determined by execution of at least one link negotiation protocol for that path.
 4. The apparatus of claim 1 wherein the initiators of the initiator-target pairs comprise respective host bus adaptors of the host device and the targets of the initiator-target pairs comprise respective storage array ports of said at least one storage system.
 5. The apparatus of claim 1 wherein said at least one processing device comprises at least a portion of the host device.
 6. The apparatus of claim 5 wherein said at least one processing device comprises a multi-path input-output driver of the host device, with the multi-path input-output driver of the host device being configured to control the delivery of the input-output operations from the host device to said at least one storage system over the selected ones of the plurality of paths through the network.
 7. The apparatus of claim 6 wherein the multi-path input-output driver is further configured to perform at least a portion of the identifying one or more of the plurality of paths that each exhibits at least a threshold amount of mismatch between a negotiated rate of its initiator and a negotiated rate of its target, and the modifying path selection in the host device to at least temporarily avoid selecting the one or more identified paths.
 8. The apparatus of claim 1 wherein said at least one processing device is further configured: to determine a first subset of the negotiated rates of initiators and targets of respective ones of the paths by communicating with said at least one storage system to obtain those negotiated rates; and to determine a second subset of the negotiated rates of initiators and targets of respective ones of the paths from an operating system of the host device.
 9. The apparatus of claim 1 wherein identifying one or more of the plurality of paths that each exhibits at least a threshold amount of mismatch between a negotiated rate of its initiator and a negotiated rate of its target comprises identifying a particular one of the paths for which the negotiated rate of its target is at least the threshold amount higher than the negotiated rate of its initiator.
 10. The apparatus of claim 1 wherein said at least one processing device is further configured to generate at least one notification for delivery to a user responsive to identifying one or more of the plurality of paths that each exhibits at least a threshold amount of mismatch between a negotiated rate of its initiator and a negotiated rate of its target.
 11. The apparatus of claim 1 wherein modifying path selection in the host device to at least temporarily avoid selecting the one or more identified paths comprises marking the one or more identified paths relative to other ones of the paths in a manner that makes the one or more identified paths less likely than those other paths to be selected by a path selection algorithm of the host device.
 12. The apparatus of claim 1 wherein modifying path selection in the host device to at least temporarily avoid selecting the one or more identified paths comprises altering a path selection algorithm of the host device to change the manner in which the one or more identified paths are considered for selection relative to other ones of the paths.
 13. The apparatus of claim 1 wherein modifying path selection in the host device to at least temporarily avoid selecting the one or more identified paths comprises at least one of: modifying the path selection only for read operations; and introducing intentional delays in one or more read operations as part of the modifying.
 14. The apparatus of claim 1 wherein said at least one processing device is further configured: to detect for at least one of the one or more identified paths a change in the negotiated rate of at least one of its initiator and its target that causes that path to exhibit less than the threshold amount of mismatch; and responsive to the detected change, to restore the modified path selection in the host device for said at least one identified path to its state prior to the modification.
 15. A method comprising: controlling delivery of input-output operations from a host device to at least one storage system over selected ones of a plurality of paths through a network, wherein the paths are associated with respective initiator-target pairs, the initiators being implemented on the host device and the targets being implemented on said at least one storage system; identifying one or more of the plurality of paths that each exhibits at least a threshold amount of mismatch between a negotiated rate of its initiator and a negotiated rate of its target; and modifying path selection in the host device to at least temporarily avoid selecting the one or more identified paths; wherein the method is performed by at least one processing device comprising a processor coupled to a memory.
 16. The method of claim 15 wherein modifying path selection in the host device to at least temporarily avoid selecting the one or more identified paths comprises modifying the path selection for a particular one of the one or more identified paths for at least a portion of a time period during which its corresponding at least threshold amount of mismatch exists.
 17. The method of claim 15 wherein modifying path selection in the host device to at least temporarily avoid selecting the one or more identified paths comprises at least one of: modifying the path selection only for read operations; and introducing intentional delays in one or more read operations as part of the modifying.
 18. A computer program product comprising a non-transitory processor-readable storage medium having stored therein program code of one or more software programs, wherein the program code, when executed by at least one processing device comprising a processor coupled to a memory, causes said at least one processing device: to control delivery of input-output operations from a host device to at least one storage system over selected ones of a plurality of paths through a network, wherein the paths are associated with respective initiator-target pairs, the initiators being implemented on the host device and the targets being implemented on said at least one storage system; to identify one or more of the plurality of paths that each exhibits at least a threshold amount of mismatch between a negotiated rate of its initiator and a negotiated rate of its target; and to modify path selection in the host device to at least temporarily avoid selecting the one or more identified paths.
 19. The computer program product of claim 18 wherein modifying path selection in the host device to at least temporarily avoid selecting the one or more identified paths comprises modifying the path selection for a particular one of the one or more identified paths for at least a portion of a time period during which its corresponding at least threshold amount of mismatch exists.
 20. The computer program product of claim 18 wherein modifying path selection in the host device to at least temporarily avoid selecting the one or more identified paths comprises at least one of: modifying the path selection only for read operations; and introducing intentional delays in one or more read operations as part of the modifying. 